High-Level Simulations of On-Chip Networks

The International Technology Roadmap for Semiconductors [1] prognoses up to four billion transistors on a single chip with feature sizes below 45 nm operating in the 10 GHz range. This will be achieved by continuous scaling of transistor dimensions and offers the opportunity to further increase the performance into the Tera-Flop era. Unfortunately, the scaling is about to approach physical limits which causes new challenges and serious problems that endanger the future development. Such issues emerge at diverse abstraction levels and they have to be considered during all design and production steps. Leakage currents, power density, clock distribution, reliability, verification, memory-bottleneck, and design-productivity-gap are just an extract of all these issues. Network-On-Chip (NOC) has been proposed as a new design methodology to cope with these problems [2]. NOCs consist of heterogeneous resources that are encapsulated from another which allows the use of different voltages, frequencies or even diverse technologies for each resource. Furthermore, encapsulation eases the exchange and reuse of resources as well as the integration of intellectual property (i.e. predefined macro blocks). The independent resources are connected (by a determined interface) to an on-chip network which affords the communication among the resources whereas the network consists of routers and physical links. An example of two possible topologies with the mentioned components is given in figure 1. Up to date, large effort has already been put into the development of elementary modules to operate NOCs in principle. For instance repeater, booster, and phase coding have been suggested for signal transmission, coding and error correction schemes have been analyzed as well as bufferless or asynchronous routers have been integrated in various topologies (e.g. mesh, torus, fat-tree) applying diverse routing schemes (e.g. XY, adaptive, deflective). First prototypes have also been produced and their functionality has successfully been proven [3][4]. However, those prototypes are application specific NOCs with a limited number of resources so that a multitude of issues of future general purpose NOCs with several hundred resources, as predicted by [5] and others, does not have to be considered. Because corresponding technologies to implement such large NOCs are not available yet and the expenditure of time as well as the cost-value ratio of large functional testchips is also questionable, the behavior of NOCs needs to be simulated to obtain results for performance, power, area, and further network related metrics like bandwidth usage or areas of increased packet congestion. Such simulations are necessary both for designers to exploit different hardware architectures and solutions as well as for vendors to evaluate different existing chips for their application-specific domains.